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product specification ps021418-0208 crimzon ? zlr16300 z8 ? low-voltage rom mcus with infrared timers copyright ? 2008 by zilog ? , inc. all rights reserved. www.zilog.com
ps021418-0208 do not use in life support life support policy zilog's products are not authorized fo r use as critical components in life support devices or systems without th e express prior written approval of the president and general counsel of zilog corporation. as used herein life support devices or systems are devices which (a) ar e intended for surgical implant into the body, or (b) support or sustain life and whose failure to perform when properly used in accordan ce with instructions for use provided in the labeling can be re asonably expected to result in a significant injury to the user. a critical component is any component in a life suppor t device or system whose failure to perform can be reasonably expected to cause the fa ilure of the life support device or system or to affect its safety or effectiveness. document disclaimer ?2008 by zilog, inc. all rights reserved. information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. zilog, inc. does not assume liability for or provide a representation of accuracy of the information, devices, or technology described in this document. zilog also does not assume liability for intellectual property infringement related in any manner to use of information, devices, or technology described herein or otherwise. the information contained within this document has been verified according to the general pr inciples of electrical and mechanical engineering. z8, z8 encore!, z8 encore! xp, z8 encore! mc, crimzon, ez80, and zneo are trademarks or registered trademarks of zilog, inc. all other product or servi ce names are the property of their respective owners. warning:
crimzon ? zlr16300 product specification ps021418-0208 revision history iii revision history each instance in the revision hi story table reflects a change to this document from its pre- vious revision. for more details , refer to the corresponding pa ges and appropriate links in the table below. date revision level description page no february 2008 18 updated the ordering information section. 85 january 2008 17 updated the ordering information section. 85 august 2007 16 updated the disclaimer section and implemented style guide. all february 2007 15 updated low-voltage detection . 54 april 2006 14 added pin p22 to the smr block input, figure 30 . 48 december 2005 13 updated input output port and clock. 12, 47
crimzon ? zlr16300 product specification ps021418-0208 table of contents iv table of contents architectural overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 expanded register file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 register file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 counter/timer functional blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 input circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 port configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 stop mode recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 watchdog timer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 low-voltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 expanded register file control registers (0d) . . . . . . . . . . . . . . . . . . . . . 55 expanded register file control registers (0f) . . . . . . . . . . . . . . . . . . . . . . 61 standard control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 standard test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 part number description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 customer support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
ps021418-0208 architectural overview crimzon ? zlr16300 product specification 1 architectural overview zilog?s crimzon ? zlr16300 mcu is a rom-based member of the crimzon zlr16300 family of general-purpose microcontrollers. with 1 kb to 16 kb of program memory and 237 b of general-purpose ram, zilog?s cmos microcontrollers offer fast-executing, efficient use of memory, sophisticated interrupts, input/output (i/o) bit manipulation capabilities, automated pulse generation/re ception, and internal key-scan pull-up transistors. the crimzon zlr16300 architecture (see figure 1 on page 3 and figure 2 on page 4) is based on zilog?s 8-bit microc ontroller core with an expand ed register file allowing access to register-mapped peripherals, i/o ci rcuits, and powerful coun ter/timer circuitry. the z8 ? core offers a flexible i/o scheme, an efficient register and address space structure, and a number of ancillary featur es that are useful in many consumer, automotive, computer peripheral, and ba ttery-operated hand-held applications. there are three basic address spaces available to support a wide range of configurations: 1. program memory 2. register file 3. expanded register file the register file is composed of 256 b of ra m. it includes three i/ o port registers, 16 control and status registers, and 237 general-pu rpose registers. the expanded register file consists of two additional register groups (f and d). to unburden the program from coping with such real-time problems like generating complex waveforms or receiving and de modulating complex waveform/pulses, the crimzon zlr16300 offers a new intelligent counter/timer architecture with 8-bit and 16-bit counter/timers (see figure 2 on page 4). also included are a large number of user-selectable modes and two on-board comp arators to process analog signals with separate reference voltages. features table 1 lists the features of crimzon zlr16300 family. table 1. crimzon zlr16300 rom mcu features device rom (kb) ram* (bytes ) i/o lines voltage range crimzon zlr16300 1, 2, 4, 8, 16 237 24, 16 2.0?3.6 v *general-purpose
ps021418-0208 architectural overview crimzon ? zlr16300 product specification 2 the additional features include: ? low power consumption?5 mw (typical) ? three standby modes: ? stop?1.3 a (typical) ? halt?0.5 ma (typical) ? low-voltage reset ? special architecture to automate both ge neration and reception of complex pulses or signals: ? one programmable 8-bit counter/timer wi th two capture registers and two load registers ? one programmable 16-bit counter/timer with one 16-bit capture register pair and one 16-bit load register pair ? programmable input glitch filter for pulse reception ? six priority interrupts ? three external ? two assigned to counter/timers ? one low-voltage detection interrupt ? low-voltage detection and hi gh-voltage detection flags ? programmable watchdog timer (wdt) ? power-on reset (por) ? two independent comparators with programmable interrupt polarity ? selectable pull-up transistors on ports 0, 2, and 3 ? mask options ? port 0: 0?3 pull-ups ? port 0: 4?7 pull-ups ? port 2: 0?7 pull-ups ? port 3: 0?3 pull-ups ? watchdog timer at power-on reset power connections use the conven tional descriptions listed in table 2 . table 2. power connections connection circuit device power v cc v dd ground gnd v ss
ps021418-0208 architectural overview crimzon ? zlr16300 product specification 3 functional block diagram figure 1 displays the crimzon zlr16300 mcu functional block diagram. figure 1. crimzon zlr16300 mcu functional block diagram z8? core port 2 port 0 p21 p22 p23 p24 p25 p26 p27 p20 i/o bit programmable p04 p05 p06 p07 p00 p01 p02 p03 i/o nibble programmable register file 256 x 8-bit register bus internal address bus internal data bus expanded register file expanded register bus z8 core counter/timer 8 8-bit counter/timer 16 16-bit v dd v ss xtal pref1/p30 p31 p32 p33 p34 p35 p36 p37 port 3 machine timing & instruction control power 4 4 rom up to 16k x 8 watchdog timer low-voltage detection high-voltage detection power-on reset note: refer to the specific package for available pins.
ps021418-0208 architectural overview crimzon ? zlr16300 product specification 4 figure 2. counter/timers diagram hi16 lo16 16-bit t16 tc16h tc16l hi8 lo8 and/or logic clock divider glitch filter edge detect circuit 8-bit t8 tc8h tc8l 8 8 16 8 input sclk 1 2 48 timer 16 timer 8/16 timer 8 8 8 8 8 8
ps021418-0208 pin description crimzon ? zlr16300 product specification 5 pin description the pin configuration for the 20-pin dip/soic/ssop is displayed in figure 3 and described in table 3 . the pin configuration for the 28-pin dip/soic/ssop are displayed in figure 4 on page 6 and described in table 4 on page 6. figure 3. 20-pin dip/soic /ssop pin configuration table 3. 20-pin dip/soic/ssop pin identification pin no symbol function direction 1?3 p25?p27 port 2, bits 5,6,7 input/output 4 p07 port 0, bit 7 input/output 5v dd power supply 6 xtal2 crystal oscillator clock output 7 xtal1 crystal oscillator clock input 8?10 p31?p33 port 3, bits 1,2,3 input 11,12 p34, p36 port 3, bits 4,6 output 13 p00/pref1/p30 port 0, bi t 0/analog reference input port 3, bit 0 input/output for p00 input for pref1/p30 14 p01 port 0, bit 1 input/output 15 v ss ground 16?20 p20?p24 port 2, bits 0,1,2,3,4 input/output p25 p26 p27 p07 v dd xtal2 xtal1 p31 p32 p33 p24 p23 p22 p21 p20 vss p01 p00/pref1/p30 p36 p34 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 20-pin dip soic ssop
ps021418-0208 pin description crimzon ? zlr16300 product specification 6 figure 4. 28-pin dip/soic/ssop pin configuration table 4. 28-pin dip/soic/ssop pin identification pin no symbol function direction 1-3 p25-p27 port 2, bits 5,6,7 input/output 4-7 p04-p07 port 0, bits 4,5,6,7 input/output 8v dd power supply 9 xtal2 crystal, oscillator clock output 10 xtal1 crystal, oscillator clock input 11?13 p31-p33 port 3, bits 1,2,3 input 14 p34 port 3, bit 4 output 15 p35 port 3, bit 5 output 16 p37 port 3, bit 7 output 17 p36 port 3, bit 6 output 18 pref1 analog ref input; connect to v cc if not used port 3 bit 0 input 19-21 p00-p02 port 0, bits 0,1,2 input/output 22 v ss ground 23 p03 port 0, bit 3 input/output 24-28 p20-p24 port 2, bits 0-4 input/output p24 p23 p22 p21 p20 p03 v ss p02 p01 p00 pref1/p30 p36 p37 p35 p25 p26 p27 p04 p05 p06 p07 v dd xtal2 xtal1 p31 p32 p33 p34 1 28-pin pdip soic ssop 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15
ps021418-0208 pin description crimzon ? zlr16300 product specification 7 pin functions xtal1 crystal 1 (time-based input) this pin connects a parallel-resonant crystal or ceramic resonator to the on-chip oscillator input. additionally, an external single-pha se clock can be connected to the on-chip oscillator input. xtal2 crystal 2 (time-based output) this pin connects a parallel-resonant crystal or ceramic resonant to the on-chip oscillator output. input/output ports the cmos input buffer for each ports 0, 1, or 2 pin is always connected to the pin, even when the pin is configured as an output. if the pin is configured as an open-drain output and no external signal is applied, a high output state causes the cmos input buffer to float. this leads to excessive le akage current of more than 100 a. to prevent this leakage, connect the pin to an external signal with a de fined logic level or ensure its output state is low, especially during stop mode. internal pull-ups are disabled on any given pin or group of port pins when programmed into output mode. port 0, 1, and 2 have both input and output capability. the input logic is always present no matter whether the port is configured as input or output. while performing a read instruction, the mcu reads the actual value at the input logic but not from the output buffer. in addition, the instructions of or, and, and xor have the read-modify-write sequence. the mcu first reads the port, mod ifies the value, and lo ads back to the port. precaution must be taken if the port is config ured as open-drain output or if the port is driving any circuit that makes the voltage di fferent from the desired output logic. for example, pins p00?p07 are not connected to anything else. if it is configured as open- drain output with output logic as one, it is a floating port and re ads back as zero. the following instruction sets p00-p07 all low. and p0,#%f0 caution:
ps021418-0208 pin description crimzon ? zlr16300 product specification 8 port 0 (p07?p00) port 0 is an 8-bit, bidirect ional, and cmos-compatible port . these eight i/o lines are con- figured under software control as a nibble i/ o port. the output drivers are push-pull or open-drain controlled by bit d2 in the pcon register. if one or both nibbles are required for i/o oper ation, they must be configured by writing to the port 0 mode register. after a hardwa re reset, port 0 is configured (see figure 5 ) as an input port. an optional pull-up transistor is available as a mask option on all port 0 bits with nibble select. the port 0 direction is reset to be in put following an stop mode recovery. figure 5. port 0 configuration note: 4 4 zlr16300 port 0 (i/o) pad in out i/o open-drain resistive transistor pull-up v cc mask option
ps021418-0208 pin description crimzon ? zlr16300 product specification 9 port 2 (p27?p20) port 2 is an 8-bit, bidirectional, and cmos-compatible i/o port (see figure 6 ). these eight i/o lines are independently configured un der software control as inputs or outputs. port 2 is always available for i/o opera tion. a mask option connects eight pull-up transistors on this port. bits programmed as outputs are globally programmed as either push-pull or open-drain. the po r resets with the eight bits of port 2 configured as inputs. port 2 also has an 8-bit input or and and gate which can be used to wake up the part. p20 is programmed to access the edge-detection circuitry in demodulation mode. figure 6. port 2 configuration port 2 (i/o) pad in out i/o open-drain resistive transistor pull-up v cc mask option zlr16300 rom
ps021418-0208 pin description crimzon ? zlr16300 product specification 10 port 3 (p37?p30) port 3 is an 8-bit, cmos-c ompatible fixed i/o port (see figure 7 ). port 3 consists of four fixed input (p33?p30) and four fixed output (p37?p34), which are configured under software control for interrupt and as output from the counter/timers. p30, p31, p32, and p33 are standard cmos inputs; p34, p35, p36, and p37 are push-pull outputs. figure 7. port 3 configuration - port 3 (i/o) p32 (an2) p31 (an1) pref1 from stop mode recovery source of smr irq2, p31 data latch pref1/p30 p31 p32 p33 p34 p35 p36 p37 d1 1 = analog 0 = digital r247 = p3m + - + irq0, p32 data latch irq1, p33 data latch comp 1 comp2 dig. an. zlr16300 rom p33 (ref2)
ps021418-0208 pin description crimzon ? zlr16300 product specification 11 two on-board comparators process analog signal s on p31 and p32, with reference to the voltage on pref1 and p33. the analog function is enabled by programming the port 3 mode register (bit 1). p31 and p32 are prog rammable as rising, falling, or both edge triggered interrupts (irq register bits 6 and 7) . pref1 and p33 are the comparator reference voltage inputs. access to the counter timer edge-detection circuit is through p31 or p20 (see t8 and t16 common functions?ctr1(0d)01h on page 24). other edge detect and irq modes are described in table 5 . comparators are powered down by entering stop mode. for p31?p33 to be used in a smr source, these inputs must be placed into digital mode. 2 port 3 also provides output for each of the counter/timers and the and/or logic (see figure 8 ). control is performed by programming bits d5?d4 of ctr1, bit 0 of ctr0, and bit 0 of ctr2. table 5. port 3 pin function summary pin i/o counter/timers comparator interrupt pref1/p30 in rf1 p31 in in an1 irq2 p32 in an2 irq0 p33 in rf2 irq1 p34 out t8 ao1 p35 out t16 p36 out t8/16 p37 out ao2 p20 i/o in note:
ps021418-0208 pin description crimzon ? zlr16300 product specification 12 figure 8. port 3 counter/ti mer output configuration pad p34 comp 1 v dd mux pcon, d0 mux ctr0, d0 p31 p30 (pref 1) p34 data t8_out + pad p35 v dd mux ctr2, d0 out 35 t16_out pad p36 v dd mux ctr1, d6 out 36 t8/t16_out pad p37 v dd mux pcon, d0 p37 data - p31 p3m d1 comp 2 p32 p33 + - p32 p3m d1
ps021418-0208 pin description crimzon ? zlr16300 product specification 13 comparator inputs in analog mode, p31 and p32 have a comparator front end. the comparator reference is supplied to p33 and p ref1 . in this mode, the p33 in ternal data latch and its corresponding irq1 are diverted to the smr sources (excluding p31, p32, and p33) as displayed in figure 7 on page 10. in digital mode, p33 is used as d3 of the port 3 input register, which then generates irq1. comparators are powered down by entering stop mode. for p31?p33 to be used in a stop mode recovery source, these inputs must be placed into digital mode. comparator outputs these channels are programmed to be output on p34 and p37 through the pcon register. note:
ps021418-0208 pin description crimzon ? zlr16300 product specification 14
ps021418-0208 functional description crimzon ? zlr16300 product specification 15 functional description the crimzon zlr16300 family of devices inco rporate special functio ns to enhance the functionality of z8 ? in consumer and battery-operated applications. program memory these devices address from 1 kb to 16 kb of program memory. the first 12 bytes are reserved for interrupt vectors. these loca tions contain the six 16-bit vectors that correspond to the six available interrupts. see figure 9 on page 16.
ps021418-0208 functional description crimzon ? zlr16300 product specification 16 ram the crimzon zlr16300 product family features 237 bytes of ram. figure 9. program memory map on-chip rom reset start address irq5 irq5 irq4 irq4 irq3 irq3 irq2 irq2 irq1 irq1 irq0 irq0 12 11 10 9 8 7 6 5 4 3 2 1 0 maximum rom size location of first byte of instruction executed after reset interrupt vector (lower byte) interrupt vector (upper byte) not accessible
ps021418-0208 functional description crimzon ? zlr16300 product specification 17 expanded register file the register file has been expa nded to allow for additional sy stem control registers and for mapping additional peripheral devices into the register address area. the z8 register address space (0 through15 (ofh)) has been impl emented as 16 banks, with 16 registers per bank. these register banks are known as th e erf (expanded register file). bits 7?4 of register rp select the working register group. bits 3?0 of register rp select the expanded register file bank. an expanded register bank is also referr ed to as an expanded register group (see figure 10 on page 18 ). note:
ps021418-0208 functional description crimzon ? zlr16300 product specification 18 figure 10. expanded register file architecture uuuuuuu0 00000000 00000000 00000000 00 0f 7f f0 ff ff spl 00000000 uuuuuuuu 00000000 uuuuuuuu uuuuuuuu uuuuuuuu 11111111 00000000 11001111 uuuuuuuu uuuuuuuu uuuuuuuu uuuuuuuu uuuuuuuu fe sph fd rp fc flags fb imr fa irq f9 ipr f8 p01m f7 p3m f6 p2m f5 reserved f4 reserved f3 reserved f2 reserved f1 reserved f0 reserved d7 d6 d5 d4 d3 d2 d1 d0 uu001101 u01000u0 11111110 (f) 0f wdtmr (f) 0e reserved (f) 0d smr2 (f) 0c reserved (f) 0b smr (f) 0a reserved (f) 09 reserved (f) 08 reserved (f) 07 reserved (f) 06 reserved (f) 05 reserved (f) 04 reserved (f) 03 reserved (f) 02 reserved (f) 01 reserved (f) 00 pcon 76543210 expanded register bank pointer working register uuuuuuuu uuuuuuuu 00000000 (d) 0c lvd (d) 0b hi8 (d) 0a lo8 (d) 09 hi16 (d) 08 lo16 (d) 07 tc16h (d) 06 tc16l (d) 05 tc8h (d) 04 tc8l (d) 03 ctr3 (d) 02 ctr2 (d) 01 ctr1 (d) 00 ctr0 group pointer register file (bank 0)** 00011111 * * 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 u = unknown. *is not reset with a stop mode recovery. **all addresses are in hexadecimal. is not reset with a stop mode recovery, except bit 0. bit 5 is not reset with a stop mode recovery. bits 5,4,3,2 not reset with a stop mode recovery. bits 5 and 4 not reset with a stop mode recovery. bits 5,4,3,2,1 not reset with a stop mode recovery. expanded reg. bank 0/group (0) (0) 03 p3 (0) 02 p2 0 u u * * * * * * * * * * * expanded reg. bank f/group 0** register** register pointer z8 standard control registers expanded reg. bank d/group 0 reset condition u (0) 00 p0 reserved note: a write has no effect. will always read back ff. note
ps021418-0208 functional description crimzon ? zlr16300 product specification 19 the upper nibble of the register pointer (see figure 11 ) selects which working register group, of 16 bytes in the register file, is a ccessed out of the possible 256. the lower nibble selects the expanded register file bank an d in the case of the crimzon zlr16300 family, banks 0, f, and d are implemented. a 0h in the lower nibble allows the normal register file (bank 0) to be addressed. any other value from 1h to fh exchanges the lower 16 reg- isters to the selected expanded register bank. figure 11. register pointer example : (see figure 10 on page 18) r253 rp = 00h r0 = port 0 r2 = port 2 r3 = port 3 but if: r253 rp = 0dh r0 = ctr0 r1 = ctr1 r2 = ctr2 r3 = ctr3 the counter/timers are mapped into erf grou p d. access is easily performed using the following: ld rp, #0dh ;select erf d for access to bank d ;(working register group 0) ld r0,#xx ;load ctr0 r253 rp d7 d6 d5 d4 d3 d2 d1 d0 expanded register file pointer working register pointer default setting after reset = 0000 0000
ps021418-0208 functional description crimzon ? zlr16300 product specification 20 ld 1, #xx ;load ctr1 ld r1, 2 ;ctr2 ctr1 ld rp, #0dh ;select erf d for access to bank d ; (working register group 0) ld rp, #7dh ;select expanded register bank d and working ;register group 7 of bank 0 for access. ld 71h, 2 ;ctrl2 register 71h ld r1, 2 ;ctrl2 register 71h register file the register file (bank 0) consists of three i/o port registers, 237 general-purpose regis- ters, 16 control and status registers (r0, r2, r3, r4?r239, and r240?r255, respectively), and two expanded register banks d (see table 6 on page 23) and f. instructions can access registers directly or indirectly through an 8- bit address field, thereby allowing a short, 4- bit register address to use the register pointer (see figure 12 on page 21). in the 4-bit mode, the register file is divided into 16 working register groups, each occupying 16 con- tinuous locations. the register pointer address es the starting location of the active work- ing register group. register address e0h?efh can be accessed only through working registers and indirect addressing modes. note:
ps021418-0208 functional description crimzon ? zlr16300 product specification 21 figure 12. register pointer?detail stack the internal register file is used for the st ack. an 8-bit stack pointer spl (r255) is used for the internal stack that resides in the ge neral-purpose registers (r4?r239). sph (r254) is used as a general-purpose register. timers t8_capture_hi?hi8(0d)0bh this register stores the captured data from th e output of the 8-bit counter/timer0. typi- cally, this register holds the number of counts when the input signal is 1. field bit position description t8_capture_hi [7:0] r/w captured data?no effect r 7 r 6 r 5 r 4 r 3 r 2 r 1 the upper nibble of the register file address provided by the register pointer specifies the active working-register group. specified working register group register group 1 register group 0 i/o ports r253 the lower nibble of the register file address provided by the instruction points to the specified * rp = 00: selects register bank 0, working register group 0 r15 to r0 r15 to r4 * r3 to r0 * 40 3f 30 2f 20 1f 10 0f 00 register group 2 4f ff f0
ps021418-0208 functional description crimzon ? zlr16300 product specification 22 t8_capture_lo?l08(0d)0ah this register holds the captured data from th e output of the 8-bit counter/timer0. typi- cally, this register holds the number of counts when the input signal is 0. t16_capture_hi?hi16(0d)09h this register holds the captured data from th e output of the 16-bit counter/timer16. this register holds the ms-byte of the data. t16_capture_lo?l016(0d)08h this register holds the captured data from th e output of the 16-bit counter/timer16. this register holds the ls-byte of the data. counter/timer2 ms-byte hold register?tc16h(0d)07h counter/timer2 ls-byte hold register?tc16l(0d)06h field bit position description t8_capture_l0 [7:0] r/w captured data?no effect field bit position description t16_capture_hi [7:0] r/w captured data?no effect field bit position description t16_capture_lo [7:0] r/w captured data?no effect field bit position description t16_data_hi [7:0] r/w data field bit position description t16_data_lo [7:0] r/w data
ps021418-0208 functional description crimzon ? zlr16300 product specification 23 counter/timer8 high hold register?tc8h0(d)05h counter/timer8 low hold register?tc8l(0d)04h ctr0 counter/timer8 control register?ctr0(0d)00h table 6 lists and briefly describes the fields for this register. field bit position description t8_level_hi [7:0] r/w data field bit position description t8_level_lo [7:0] r/w data table 6. ctr0(0d)00h counter/timer8 control register field bit position value description t8_enable 7------- r/w 0* 1 0 1 counter disabled counter enabled stop counter enable counter single/modulo-n -6------- r/w 0* 1 modulo-n single-pass time_out --5------ r/w 0** 1 0 1 no counter time-out counter time-out occurred no effect reset flag to 0 t8 _clock ---43--- r/w 0 0** 0 1 1 0 1 1 sclk sclk/2 sclk/4 sclk/8 capture_int_mask -----2-- r/w 0** 1 disable data capture interrupt enable data capture interrupt counter_int_mask ------1- r/w 0** 1 disable time-out interrupt enable time-out interrupt p34_out -------0 r/w 0* 1 p34 as port output t8 output on p34 * indicates the value at power-on reset. * *indicates the value upon power-on reset. not reset with a stop mode recovery.
ps021418-0208 functional description crimzon ? zlr16300 product specification 24 t8 enable this field enables t8 when set to 1. single/modulo-n when set to 0 (modulo-n), the counter reloads the initia l value when the terminal count is reached. when set to 1 (single-pass), the counter stops when the terminal count is reached. timeout this bit is set when t8 times ou t (terminal count reached). to r eset this bit, write a 1 to its location. writing a 1 is the only way to reset the term inal count status condition. reset this bit before using/enabling the counter/timers. the first clock of t8 might not have comp lete clock width and can occur any time when enabled. ensure to manipulate c tr0, bit 5 and ctr1, bits 0 and 1 (demodulation mode) while using the or or and commands. th ese instructions use a read-modify-write sequence in which the current status from the ctr0 and ctr1 registers is ored or anded with the designated value and th en written back into the registers. t8 clock these bits define the frequency of the input signal to t8. capture_int_mask set this bit to allow an interrupt when data is captured into either lo8 or hi8 upon a posi- tive or negative edge detection in capture mode. counter_int_mask set this bit to allow an interrupt when t8 has a timeout. p34_out this bit defines whether p34 is used as a normal output pin or the t8 output. t8 and t16 common functions?ctr1(0d)01h this register controls the functions common with the t8 and t16. table 7 lists and briefly describes the fields for this register. caution: note:
ps021418-0208 functional description crimzon ? zlr16300 product specification 25 table 7. ctr1(0d)01h t8 and t16 common functions field bit position value description mode 7------- r/w 0* 1 transmit mode demodulation mode p36_out/ capture_input -6------ r/w 0* 1 0* 1 transmit mode port output t8/t16 output demodulation mode p31 p20 t8/t16_logic/ edge _detect --54---- r/w 00** 01 10 11 00** 01 10 11 transmit mode and or nor nand demodulation mode falling edge rising edge both edges reserved transmit_submode/ glitch_filter ----32-- r/w 00 01 10 11 00 01 10 11 transmit mode normal operation ping-pong mode t16_out = 0 t16_out = 1 demodulation mode no filter 4 sclk cycle 8 sclk cycle reserved initial_t8_out/ rising edge ------1- r/w r w 0 1 0 1 0 1 transmit mode t8_out is 0 initially t8_out is 1 initially demodulation mode no rising edge rising edge detected no effect reset flag to 0
ps021418-0208 functional description crimzon ? zlr16300 product specification 26 mode if the result is 0, the counter/timers are in transmit mode, else, they are in demodu- lation mode. p36_out/demodulator_input in transmit mode, this bit defines whether p36 is used as a normal output pin or the combined output of t8 and t16. in demodulation mode, this bit defines wh ether the input signal to the counter/tim- ers is from p20 or p31. if the input signal is from port 31, a capture event generates an irq2 interrupt. to prevent generating an irq2, either disable the irq2 in terrupt by clearing its imr bit d2 or use p20 as the input. t8/t16_logic/edge_detect in transmit mode, this field defines how the outputs of t8 and t16 are combined (and, or, nor, nand). in demodulation mode, this field defines wh ich edge is detected by the edge detec- tor. transmit_submode/glitch filter in transmit mode, this field defines whethe r t8 and t16 are in the ping-pong mode or in independent normal operation mode. se tting this field to ?normal operation mode? terminates the ?ping-pong mode ? operation. when set to 10, t16 is immediately forced to a 0; a setting of 11 forces t16 to output a 1. in demodulation mode, this field defines the width of the glitch th at must be filtered out. initial_t16_out/ falling_edge -------0 r/w r w 0 1 0 1 0 1 transmit mode t16_out is 0 initially t16_out is 1 initially demodulation mode no falling edge falling edge detected no effect reset flag to 0 *default at power-on reset. *indicates the value upon power-on reset. not reset with a stop mode recovery. table 7. ctr1(0d)01h t8 and t16 common functions (continued) field bit position value description
ps021418-0208 functional description crimzon ? zlr16300 product specification 27 initial_t8_out/rising_edge in transmit mode, if 0, the output of t8 is set to 0 when it starts to count. if 1, the out- put of t8 is set to 1 when it starts to count. when the counter is not enabled and this bit is set to 1 or 0, t8_out is set to the opposite st ate of this bit. this ensures that when the clock is enabled, a transition occurs to the initial state set by ctr1, d1. in demodulation mode, this bit is set to 1 wh en a rising edge is detected in the input signal. in order to reset the mode, a 1 should be written to this location. initial_t16 out/falling _edge in transmit mode, if it is 0, the output of t1 6 is set to 0 when it starts to count. if it is 1, the output of t16 is set to 1 when it starts to count. this bit is effective only in nor- mal or ping-pong mode (ctr1, d3; d2). when the counter is not enabled and this bit is set, t16_out is set to the oppo site state of this bit. this ensures that when the clock is enabled, a transition occurs to the initial state set by ctr1, d0. in demodulation mode, this bit is set to 1 when a falling edge is detected in the input signal. in order to reset it, a 1 should be written to this location. modifying ctr1 (d1 or d0) wh ile the counters are enabled causes unpredictable output from t8/16_out. ctr2 counter/timer 16 control register?ctr2(0d)02h table 8 lists and briefly describes the fields for this register. table 8. ctr2(0d)02h: counter/timer16 control register field bit position value description t16_enable 7------- r w 0* 1 0 1 counter disabled counter enabled stop counter enable counter single/modulo-n -6------ r/w 0 1 0 1 transmit mode modulo-n single pass demodulation mode t16 recognizes edge t16 does not recognize edge time_out --5----- r w 0** 1 0 1 no counter timeout counter timeout occurred no effect reset flag to 0 note:
ps021418-0208 functional description crimzon ? zlr16300 product specification 28 t16_enable this field enables t16 when set to 1. single/modulo-n in transmit mode, when set to 0, the counter reloads th e initial value when it reaches the terminal count. when set to 1, the counter stops when th e terminal count is reached. in demodulation mode, when set to 0, t16 captures and reloads on detection of all the edges. when set to 1, t16 captures and de tects on the first edge but ignores the subse- quent edges. for details, see t16 demodulation mode on page 37. time_out this bit is set when t16 times out (terminal count reached). to reset the bit, write a 1 to this location. t16_clock this bit defines the frequency of th e input signal to counter/timer16. capture_int_mask this bit is set to allow an interrupt when data is cap tured into lo16 and hi16. counter_int_mask set this bit to allow an interrupt when t16 times out. t16 _clock ---43--- r/w 00** 01 10 11 sclk sclk/2 sclk/4 sclk/8 capture_int_mask -----2-- r/w 0** 1 disable data capture int. enable data capture int. counter_int_mask ------1- r/w 0* disable timeout int. enable timeout int. p35_out -------0 r/w 0* 1 p35 as port output t16 output on p35 *indicates the value upon power-on reset. **indicates the value upon power-on reset. not reset with a stop mode recovery. table 8. ctr2(0d)02h: counter/timer16 control register (continued) field bit position value description
ps021418-0208 functional description crimzon ? zlr16300 product specification 29 p35_out this bit defines whether p35 is used as a normal output pin or t16 output. ctr3 t8/t16 control register?ctr3(0d)03h table 9 lists and briefly describes the fields for this register. this register allow the t8 and t16 counters to be synchronized. counter/timer functional blocks input circuit the edge detector monitors the input signal on p31 or p20. based on ctr1 d5?d4, a pulse is generated at the pos edge or neg edge line when an edge is detected. glitches in the input signal that have a width less than specified (ctr1 d3, d2) are filtered out (see figure 13 ). table 9. ctr3(0d)03h t8/t16 control register t16_enable 7------- r r w w 0* 1 0 1 counter disabled counter enabled stop counter enable counter t8 enable -6------ r/w 0** 1 0 1 counter disabled counter enabled stop counter enable counter sync mode --5----- r/w 0* 1 disable sync mode enable sync mode reserved ---43210 r/w 1 x always reads 11111 no effect * indicates the value upon power-on reset. * **indicates the value upon power-on reset. not reset with a stop mode recovery.
ps021418-0208 functional description crimzon ? zlr16300 product specification 30 figure 13. glitch filter circuitry t8 transmit mode before t8 is enabled, the output of t8 depend s on ctr1, d1. if it is 0, t8_out is 1; if it is 1, t8_out is 0. see figure 14 on page 31. mux glitch filter edge detector p31 p20 pos edge neg edge ctr1 d5,d4 ctr1 d6 ctr1 d3, d2
ps021418-0208 functional description crimzon ? zlr16300 product specification 31 figure 14. transmit mode flowchart set timeout status bit (ctr0 d5) and generate timeout_int if enabled set timeout status bit (ctr0 d5) and generate timeout_int if enabled t8 (8-bit) transmit mode no t8_enable bit set ctr0, d7 yes ctr1, d1 value reset t8_enable bit 0 1 load tc8l reset t8_out load tc8h set t8_out enable t8 no t8_timeout yes single pass single modulo-n t8_out value 0 enable t8 no t8_timeout ye s pass? load tc8h set t8_out load tc8l reset t8_out 1
ps021418-0208 functional description crimzon ? zlr16300 product specification 32 when t8 is enabled, the outp ut t8_out switches to the initial value (ctr1, d1). if the initial value (ctr1, d1) is 0, tc8l is loaded , else, tc8h is loaded into the counter. in single-pass mode (ctr0, d6), t8 counts do wn to 0 and stops, t8_out toggles, the timeout status bit (ctr0, d5) is set, and a timeout interrupt can be generated if it is enabled (ctr0, d1). in modu lo-n mode, upon reaching terminal count, t8_out is toggled, but no interrupt is generated. fr om that point, t8 loads a new count (if the t8_out level now is 0), tc8l is loaded; if it is 1, tc8h is loaded. t8 counts down to 0, toggles t8_out, and sets the timeout status bit (ctr0, d5), thereby generating an inter- rupt if enabled (ctr0, d1). one cycle is complete. t8 then loads from tc8h or tc8l according to the t8_out leve l and repeats the cycle. see figure 15 . figure 15. 8-bit counter/timer circuits the values in tc8h or tc8l can be modified at any time. the new values take effect when they are loaded. to ensure known operation do not write these registers at the time the values are to be loaded into the counte r/timer. an initial count of 1 is not allowed (a non-function oc- curs). an initial count of 0 caus es tc8 to count from 0 to ffh to feh . the letter h denotes hexadecimal values. transition from 0 to ffh is not a timeout condition. ctr0 d1 negative edge positive edge z8 data bus irq4 ctr0 d2 sclk z8 data bus ctr0 d4, d3 clock t8_out lo8 tc8h tc8l clock select 8-bit counter t8 hi8 caution: note:
ps021418-0208 functional description crimzon ? zlr16300 product specification 33 using the same instructions fo r stopping the counter/timers and setting the status bits is not recommended. two successive commands are necessary. first, the counte r/timers must be stopped. sec- ond, the status bits must be reset. the se commands are required because it takes one counter/timer clock interval for the initiated event to actually occur. see figure 16 and figure 17 . figure 16. t8_out in single-pass mode figure 17. t8_out in modulo-n mode t8 demodulation mode you must program tc8l and tc8h to ffh . after t8 is enabled, when the first edge (ris- ing, falling, or both depending on ctr1, d5 ; d4) is detected, it starts to count down. when a subsequent edge (rising, falling, or bo th depending on ctr1, d5; d4) is detected during counting, the current value of t8 is complemented and put into one of the capture registers. if it is a positive edge, data is put into lo8; if it is a negative edge, data is stored in hi8. from that point, one of the edge dete ct status bits (ctr1, d1; d0) is set, and an interrupt is generated if enabled (ctr0, d2). meanwh ile, t8 is loaded with ffh and starts counting again. if t8 reaches 0, the timeout stat us bit (ctr0, d5) is set, and an interrupt caution: tc8h counts counter enable command; t8_out switches to its initial value (ctr1 d1) t8_out toggles; timeout interrupt counter enable command; t8_out switches to its initial value (ctr1 d1) timeout interrupt timeout interrupt t8_out t8_out toggles tc8l tc8h tc8h tc8l tc8l ...
ps021418-0208 functional description crimzon ? zlr16300 product specification 34 can be generated if enabled (ctr0, d1). t8 then continues counting from ffh (see figure 19 on page 35). figure 18. demodulation mode count capture flowchart t8 (8-bit) count capture t8 enable (set by user) no yes edge present what kind of edge t8 hi8 no yes negative ffh t8 positive t8 lo8
ps021418-0208 functional description crimzon ? zlr16300 product specification 35 figure 19. demodulation mode flowchart t8 (8-bit) capture mode t8 enable ctr0, d7 no yes ffh tc8 first edge present enable tc8 t8_enable bit set edge present t8 timeout set edge present status bit and trigger data capture int. if enabled set timeout status bit and trigger timeout int. if enabled continue counting disable tc8 no yes no yes yes yes no no
ps021418-0208 functional description crimzon ? zlr16300 product specification 36 t16 transmit mode in normal or ping-pong mode, the output of t16 when not enabled, is dependent on ctr1, d0. if it is a 0, t16_out is a 1; if it is a 1, t16_out is 0. you can force the output of t16 to either a 0 or 1 whether it is enab led or not by programming ctr1 d3; d2 to a 10 or 11. when t16 is enabled, tc16h * 256 + tc16l is loaded, and t16_out is switched to its initial value (ctr1, d0). wh en t16 counts down to 0, t16_out is toggled (in nor- mal or ping-pong mode), an interrupt (ctr2, d1) is generated (if enabled), and a sta- tus bit (ctr2, d5) is set. see figure 20 . figure 20. 16-bit counter/timer circuits global interrupts override this function as described in interrupts on page 40 . if t16 is in single-pass mode, it is stopped at this point (see figure 21 on page 37). if it is in modulo-n mode, it is loaded with tc16h * 256 + tc16l, and the counting continues (see figure 22 on page 37). the values in tc16h and tc16l can be modified at any time. the new values take effect when they are loaded. ctr2 d1 negative edge positive edge z8 data bus irq3 ctr2 d2 sclk z8 data bus ctr2 d4, d3 clock t16_out lo16 tc16h tc16l clock select 16-bit counter t16 hi16 note:
ps021418-0208 functional description crimzon ? zlr16300 product specification 37 do not load these registers at the time the values are to be loaded into th e counter/timer to ensure known operation. an initial count of 1 is not allowed. an initial count of 0 causes t16 to count from 0 to ffffh to fffeh . transition from 0 to ffffh is not a tim- eout condition. figure 21. t16_out in single-pass mode figure 22. t16_out in modulo-n mode t16 demodulation mode you must program tc16l and tc16h to ffh . once t16 is enabled, and the first edge (rising, falling, or both depending on ctr1 d5; d4) is detected, t16 captures hi16 and lo16, reloads, and begins counting. if d6 of ctr2 is 0 when a subsequent edge (rising , falling, or both depending on ctr1, d5; d4) is detected during counting, the current count in t16 is complemented and put into hi16 and lo16. when data is captured, one of the edge detect status bits (ctr1, d1; d0) is set, and an interrupt is generated if enabled (ctr2, d2). t16 is loaded with ffffh and starts again. this t16 mode is generally used to measure space time, the length of time between bursts of carrier signal (marks). caution: tc16h*256+tc16l counts ?counter enable? command t16_out switches to its initial value (ctr1 d0) t16_out toggles, timeout interrupt tc16h*256+tc16l tc16h*256+tc16l tc16h*256+tc16l t16_out toggles, timeout interrupt t16_out toggles, timeout interrupt ?counter enable? command, t16_out switches to its initial value (ctr1 d0) tc16_out ...
ps021418-0208 functional description crimzon ? zlr16300 product specification 38 if d6 of ctr2 is 1 t16 ignores the subsequent edges in the inpu t signal and continues counting down. a tim- eout of t8 causes t16 to capture its current value and generate an interrupt if enabled (ctr2, d2). in this case, t1 6 does not reload and continue s counting. if the d6 bit of ctr2 is toggled (by writing a 0 then a 1 to it) , t16 captures and reloads on the next edge (rising, falling, or both depend ing on ctr1, d5; d4), contin uing to ignore subsequent edges. this t16 mode generally measur es mark time, the length of an active carrier signal burst. if t16 reaches 0, t16 continues counting from ffffh . meanwhile, a status bit (ctr2 d5) is set, and an interrupt timeout is generated if enabled (ctr2 d1). ping-pong mode this operation mode is valid only in trans mit mode. t8 and t16 must be programmed in single-pass mode (ctr0, d6; ctr2, d6), and ping-pong mode must be pro- grammed in ctr1, d3; d2. you can begin the operation by enabling either t8 or t16 (ctr0, d7 or ctr2, d7). for example, if t8 is enabled, t8_out is set to this initial value (ctr1, d1). according to t8_out's level, tc8h or tc 8l is loaded into t8. after the terminal count is reached, t8 is disabled , and t16 is enabled. t16_out then switches to its initial value (ctr1, d0), data from tc 16h and tc16l is loaded, and t16 starts to count. after t16 reaches the terminal count, it stops, t8 is enabled again, repeating the entire cycle. interrupts are allowed when t8 or t16 reaches terminal control (ctr0, d1; ctr2, d1). to stop the ping-pong operation, write 00 to bits d3 and d2 of ctr1. see figure 23 . enabling ping-pong operation wh ile the counter/timers are running might cause intermit- tent counter/timer func tion. disable the counte r/timers and reset the status flags before instituting this operation. figure 23. ping-pong mode diagram note: enable tc8 enable timeout tc16 ping-pong ctr1 d3,d2 timeout
ps021418-0208 functional description crimzon ? zlr16300 product specification 39 initiating ping-pong mode ensure that both counter/timers are not runn ing. set t8 into single-pass mode (ctr0, d6), set t16 into single-pass mode (c tr2, d6), and set the ping-pong mode (ctr1, d2; d3). these instructions can be in random order. finally, start ping-pong mode by enabling either t8 (ctr0, d7) or t16 (ctr2, d7). see figure 23 on page 39. figure 24. output circuit the initial value of t8 or t16 must not be 1 . if you stop the timer and restart the timer, reload the initial value to avoid an unknown previous value. during ping-pong mode the enable bits of t8 and t16 (ctr0, d7; ctr2, d7) are set and cleared alternately by hardware. the timeout bits (ctr0, d5; ctr2 , d5) are set every time the counter/timers reach the terminal count. timer output the output logic for the timers is displayed in figure 24 . p34 is used to output t8-out when d0 of ctr0 is set. p35 is used to ou tput the value of t16-out when d0 of crtr2 is set. when d6 of ctr1 is set, p36 outp uts the logic combinatio n of t8-out and t16- out determined by d5 and d4 of ctr1. t16_out mux ctr1 d3 t8_out p34 and/or/nor/nand logic mux mux mux p35 p36 p34_internal ctr1 d5, d4 p36_internal p35_internal ctr1, d2 ctr0 d0 ctr1 d6 ctr2 d0
ps021418-0208 functional description crimzon ? zlr16300 product specification 40 interrupts the crimzon zlr16300 features six different interrupts (see table 10 on page 42). the interrupts are maskable and prioritized (see figure 25 on page 41). the six sources are divided as follows: ? three sources are claimed by port 3 lines p33?p31 ? two by the counter/timers (see table 10 on page 42) ? one for low-voltage detection the interrupt mask register (globally or indi vidually) enables or di sables the six interrupt requests. the source for irq is determined by bit 1 of the port 3 mode register (p3m). when in digital mode, pin p33 is the source. when in analog mode the output of the stop mode recovery source logic is used as the source for the interrupt. see figure 30 on page 48.
ps021418-0208 functional description crimzon ? zlr16300 product specification 41 figure 25. interrupt block diagram low-voltage detection timer 8 timer 16 interrupt edge select imr ipr priority logic irq 6 irq2 irq0 irq1 irq3 irq4 irq5 p31 p32 irq register d6, d7 global interrupt enable interrupt request vector select d1 of p3m register p33 0 1 stop mode recovery source
ps021418-0208 functional description crimzon ? zlr16300 product specification 42 when more than one interrupt is pending, pr iorities are resolved by a programmable prior- ity encoder controlled by the in terrupt priority register. an interrupt machine cycle acti- vates when an interrupt request is granted. as a result, all subsequent interrupts are disabled, and the program counter and status flags are saved. the cycl e then branches to the program memory vector location reserve d for that interrupt. all crimzon zlr16300 interrupts are vectored through locations in the program memory. this memory location and the next byte contain the 16-bit address of the interrupt service routine for that partic- ular interrupt request. to accommodate polle d interrupt systems, interrupt inputs are masked, and the interrupt request register is polled to determine which of the interrupt requests require service. an interrupt resulting from an 1 is mapped into irq2, an d an interrupt from an2 is mapped into irq0. interrupts ir q2 and irq0 can be rising, falling, or both edge trig- gered. you can program these interrupts. the so ftware can poll to identify the state of the pin. programming bits for the interru pt edge select are located in the irq register (r250), bits d7 and d6. table 11 indicates the irq configuration. table 10. interrupt types, sources, and vectors name source vector location comments irq0 p32 0,1 external (p32), rising, falling edge triggered irq1 p33 2,3 external (p33) , falling edge triggered irq2 p31, t in 4,5 external (p31), rising, falling edge triggered irq3 t16 6,7 internal irq4 t8 8,9 internal irq5 lvd 10,11 internal table 11. irq register irq interrupt edge d7 d6 irq2 (p31) irq0 (p32) 00f f 01f r 10r f 11r/f r/f note: f = falling edge; r = rising edge.
ps021418-0208 functional description crimzon ? zlr16300 product specification 43 clock the device?s on-chip oscillator has a high-gai n, parallel-resonant am plifier for connection to a crystal, ceramic resonator, or any suita ble external clock source (xtal1 = input, xtal2 = output). the crystal must be at cu t, 1 mhz to 8 mhz (maximum) with a series resistance (rs) less than or equal to 100 ? . the on-chip oscillator is driven with a suitable external clock source. the crystal must be connected across xt al1 and xtal2 using the recommended capac- itors from each pin to ground. the typi cal capacitor value is 10 pf for 8 mhz. check with the crystal supplier for the optimum capacitance. figure 26. oscillator configuration zilog?s ir mcu supports crystal, resonator, and oscillator. most r esonators have a fre- quency tolerance of less than 0.5%, which is enough for re mote control application. res- onator has a very fast startup time, which is around few hundred microseconds. most crystals have a frequency tolerance of less than 50 ppm (0.005%). however, crystal needs longer startup time than the resonato r. the large loading capacitance slows down the oscillation startup time. zilog ? suggests not to use more th an 10 pf loading capacitor for the crystal. if the stray capacitance of the pcb or the crystal is high, the loading capac- itance c1 and c2 must be reduced further to ensure stable oscillation before the t por (power-on reset time is typically 5?6 ms, see table 18 on page 76). for smr operation, bit 5 of smr register allo ws you to select the smr delay, which is the t por . if smr delay is not selected, the mcu executes instruction immediately after it wakes up from the stop mode. if resonator or crystal is used as a clock source then smr delay needs to be selected (bit 5 of smr = 1). note: c1 c2 xtal1 xtal2 xtal1 xtal2 crystal c1, c2 = 10 pf * f=8mhz external clock *note: preliminary value. xtal1 xtal2 ceramic resonator f = 8 mhz
ps021418-0208 functional description crimzon ? zlr16300 product specification 44 for both resonator and crystal oscillator, th e oscillation ground must go directly to the ground pin of the microcontroller. the oscillation ground must use the shortest distance from the microcontroller ground pin and it must be isolated from other connections. power management power-on reset a timer circuit clocked by a dedicated on-boar d rc-oscillator is used for the power-on reset timer function. the por time allows v dd and the oscillator circuit to stabilize before instruction execution begins. the por timer circuit is a one-shot time r triggered by one of three conditions: 1. power fail to power ok status, including waking up from v bo standby. 2. stop mode recovery (if d5 of smr = 1). 3. wdt timeout. the por timer is 2.5 ms minimum. bit 5 of the stop-mode register determines whether the por timer is bypassed after stop mode recovery (typical for external clock). halt mode this instruction turns off th e internal cpu clock, but not the xtal oscillation. the counter/timers and external in terrupts irq0, irq1, irq2, ir q3, irq4, and irq5 remain active. the devices are recovered by interrupts, either externally or internally generated. an interrupt request must be executed (ena bled) to exit halt mode. after the interrupt service routine, the prog ram continues from the inst ruction after the halt. stop mode this instruction turns off the internal clock and external crystal oscillation, reducing the standby current to 10 a or less. stop mode is terminated only by a reset, such as wdt timeout, por or smr. this c ondition causes the processor to restart the application pro- gram at address 000ch . in order to enter stop (or halt) mode, first flush the instruction pipeline to avoid suspending execution in mi d-instruction. execute an nop instruction (opcode = ffh ) immediately before the appropriat e sleep instruction, as follows: ff nop ; clear the pipeline 6f stop ; enter stop mode or ff nop ; clear the pipeline 7f halt ; enter halt mode
ps021418-0208 functional description crimzon ? zlr16300 product specification 45 port configuration port configuration register the port configuration (pcon) register (see figure 27 ) configures the comparator output on port 3. it is located in the expanded register file at bank f, location 00. pcon (0f) 00h figure 27. port configuration register (pcon) (write only) comparator output port 3 (d0) bit 0 controls the comparator used in port 3. a 1 in this location brings the comparator outputs to p34 and p37, and a 0 releases th e port to its standard i/o configuration. port 0 output mode (d2) bit 2 controls the output mode of port 0. a 1 in this location sets the output to push-pull, and a 0 sets the output to open-drain. stop mode recovery stop mode recovery register this register selects the clock divide value and determines the mode of stop mode recov- ery (see figure 28 on page 46). all bits are write only except bit 7, which is read only. bit d7 d6 d5 d4 d3 d2 d1 d0 comparator output port 3 0 p34, p37 standard output* 1 p34, p37 comparator output reserved (must be 1) port 0 0: open-drain 1: push-pull* reserved (must be 1) *default setting after reset.
ps021418-0208 functional description crimzon ? zlr16300 product specification 46 7 is a flag bit that is hardware set on the condition of stop recovery and reset by a power- on cycle. bit 6 controls whether a low leve l or a high level at the xor-gate input (see figure 30 on page 48) is required from the recove ry source. bit 5 controls the reset delay after recovery. bits d2, d3, and d4 of the smr register specify the source of the stop mode recovery signal. bits d0 determines if sclk/tclk are divided by 16 or not. the smr is located in bank f of the expanded register file at address 0bh . smr (0f) 0bh figure 28. stop mode recovery register sclk/tclk divide-by-16 select (d0) d0 of the smr controls a divide-by-16 prescaler of sclk/tclk (see figure 29 on page 47). this control selectively reduces device power consumption during normal processor d7 d6 d5 d4 d3 d2 d1 d0 sclk/tclk divide-by-16 0 off * * 1 on reserved (must be 0) stop mode recovery source 000 por only * 001 reserved 010 p31 011 p32 100 p33 101 p27 110 p2 nor 0-3 111 p2 nor 0-7 stop delay 0 off 1 on * * * * stop recovery level * * * 0 low * 1 high stop flag 0 por * 1 stop recovery * * *default after power-on reset or watchdog reset. * *default setting after reset and stop mode recovery. * * *at the xor gate input. * * * *default setting after reset. must be 1 if using a crystal or resonator clock source.
ps021418-0208 functional description crimzon ? zlr16300 product specification 47 execution (sclk control) and/or halt mode (where tclk sources interrupt logic). after stop mode recovery , this bit is set to 0. figure 29. sclk circuit stop mode recovery register 2?smr2(0f)0dh table 12 lists and describes the fields for this register. table 12. smr2(f)0dh:stop mode recovery register 2* field bit position value description reserved 7------- 0 reserved (must be 0) recovery level -6------ w0 ? 1 low high reserved --5----- 0 reserved (must be 0) source ---432-- w 000 ? 001 010 011 100 101 110 111 a. por only b. nand of p23?p20 c. nand of p27?p20 d. nor of p33?p31 e. nand of p33?p31 f. nor of p33?p31, p00, p07 g. nand of p33?p31, p00, p07 h. nand of p33?p31, p22?p20 reserved ------10 00 reserved (must be 0) *port pins configured as outputs are ignored as an smr recovery source. ? indicates the value at power-on reset. sclk tclk smr, d0 2 osc 16
ps021418-0208 functional description crimzon ? zlr16300 product specification 48 stop mode recovery source (d2, d3, and d4) these three bits of the smr specify the wa ke-up source of the stop recovery (see figure 30 on page 48 and table 13 on page 49). figure 30. stop mode recovery source smr2 d4 d3 d2 100 smr2 d4 d3 d2 111 smr d4d3d2 010 smr d4d3d2 111 smr d4d3d2 101 smr d4d3d2 100 smr d4d3d2 011 smr d4d3d2 000 smr d4d3d2 110 vcc p31 p32 p33 p27 p20 p23 p20 p27 smr2 d4 d3 d2 001 smr2 d4 d3 d2 000 smr2 d4 d3 d2 010 smr2 d4 d3 d2 011 smr2 d4 d3 d2 101 smr2 d4 d3 d2 110 vcc p20 p23 p20 p27 p31 p32 p33 p31 p32 p33 p31 p32 p33 p00 p31 p32 p33 p00 p31 p32 p33 p20 p21 smr d6 smr2 d6 to reset and wdt circuitry (active low)
ps021418-0208 functional description crimzon ? zlr16300 product specification 49 any port 2 bit defined as an output drives the corresponding input to the default state. this condition allows the remaining inputs to control the and/or function. for other recover sources, see stop mode recovery register 2 (smr2) . stop mode recovery delay select (d5) this bit, if low, disables the t por delay after stop mode recovery. the default configu- ration of this bit is 1. if the ?fast? wake-up is selected, the stop mode recovery source must be kept active for at least 10 tpc. this bit must be set to 1 if using a crystal or resonator clock source. the t por delay allows the clock source to stab ilize before executing instructions. stop mode recovery edge select (d6) a 1 in this bit position indicates that a high level on any one of the recovery sources wakes the crimzon zlr16300 from stop mode. a 0 indicates low level recovery. the default is 0 on por. cold or warm start (d7) this bit is read only. it is set to 1 when the device is recovered from stop mode. the bit is set to 0 when the device reset is other than smr. stop mode recovery register 2 (smr2) this register determines the mode of stop mode recovery for smr2 (see figure 31 on page 50). table 13. stop mode recovery source smr:432 operation d4 d3 d2 description of action 0 0 0 por and/or external reset recovery 001reserved 010p31 transition 011p32 transition 100p33 transition 101p27 transition 1 1 0 logical nor of p20 through p23 1 1 1 logical nor of p20 through p27 note: note:
ps021418-0208 functional description crimzon ? zlr16300 product specification 50 smr2 (0f) dh figure 31. stop mode recovery register 2 ((0f) dh:d2?d4, d6 write only) if smr2 is used in conjunctio n with smr, either of the sp ecified events causes a stop mode recovery. port pins configured as outputs are ignored as an smr or smr2 recovery source. for example, if the nand or p23?p20 is selected as the recovery source and p20 is config- ured as an output, the remaining smr pins (p23?p21) form the nand equation. d7 d6 d5 d4 d3 d2 d1 d0 reserved (must be 0) reserved (must be 0) stop mode reco very source 2 000 por only * 001 nand p20, p21, p22, p23 010 nand p20, p21, p22, p2 3, p24, p25, p26, p27 011 nor p31, p32, p33 100 nand p31, p32, p33 101 nor p31, p32, p33, p00, p07 110 nand p31, p32, p33, p00, p07 111 nand p31, p32, p33, p20, p21, p22 reserved (must be 0) recovery level * * 0low * 1 high reserved (must be 0) note: if used in conjunction with smr, either of the two specified events causes a stop mode recovery. *default setting after reset. * *at the xor gate input. note:
ps021418-0208 functional description crimzon ? zlr16300 product specification 51 watchdog timer mode watchdog timer mode register (wdtmr) the watchdog timer is a retriggerable one-shot tim er that resets the z8 if it reaches its ter- minal count. the wdt must initially be enab led by executing the wdt instruction. on subsequent executions of the wdt instruction, the wdt is refreshed. the wdt circuit is driven by an on-board rc-oscillator. the wdt instruction affects the zero (z), sign (s), and overflow (v) flags. the por clock source the internal rc-oscillator. bits 0 and 1 of the wdt register control a tap circuit that determines the minimum tim eout period. bit 2 determines whether the wdt is active during halt, and bit 3 dete rmines wdt activity during stop. bits 4 through 7 are reserved (see figure 32 ). this register is accessible only during the first 60 processor cycles (120 xtal clocks) from the execution of the first instruction after power-on reset, watchdog reset, or a stop mode recovery (see figure 31 on page 50). after this point, the register cannot be modified by any means (intentional or otherwise). the wdtmr cannot be read. the register is lo cated in bank f of the expanded register file at address location 0fh . it is organized as displayed in figure 32 . wdtmr (0f) 0fh figure 32. watchdog timer mode register (write only) d7 d6 d5 d4 d3 d2 d1 d0 wdt tap int rc osc 00 10 ms min. 01* 20 ms min. 10 40 ms min. 11 160 ms min. wdt during halt 0off 1on * wdt during stop 0off 1on * reserved (must be 0) *default setting after reset.
ps021418-0208 functional description crimzon ? zlr16300 product specification 52 wdt time select (d0, d1) this bit selects the wdt time period . it is configured as indicated in table 14 . wdtmr during halt (d2) this bit determines whether the wdt is active or not during halt mode. a 1 indicates active during halt. the default is 1. see figure 33 on page 53. table 14. watchdog timer time select d1 d0 timeout of internal rc-oscillator 0 0 10 ms min. 0 1 20 ms min. 1 0 40 ms min. 1 1 160 ms min.
ps021418-0208 functional description crimzon ? zlr16300 product specification 53 figure 33. resets and wdt wdtmr during stop (d3) this bit determines whether or not the wdt is active during stop mode. a 1 indicates active during stop. the default is 1. rom selectable options there are five rom selectable options to c hoose from based on rom code requirements. these options are listed in table 15 on page 54. - *clr1 and clr2 enable the wdt/por and 18 clock reset timers respectively upon a low-to-high input translation. + from stop mode recovery source stop delay select (smr) 5 clock filter *clr2 18 clock reset clk generator reset wdt tap select por 10 ms 20 ms 40 ms 160 ms clk *clr1 wdt/por counter chain internal rc oscillator wdt v dd low operating voltage detection vbo v dd internal reset active high 12-ns glitch filter xtal
ps021418-0208 functional description crimzon ? zlr16300 product specification 54 voltage brownout/standby an on-chip voltage comparator checks that the v dd is at the required level for correct operation of the device. reset is globally driven when v dd falls below v bo . a small drop in v dd causes the xtal1 and xtal2 circuitry to stop the crystal or resonator clock. if the v dd is allowed to stay above v ram , the ram content is preserved. when the power level is returned to above v bo , the device performs a por and functions normally. low-voltage detection low-voltage detection register?lvd(0d)0ch voltage detection does not work at stop mode. do not modify register p01m while checking a low-voltage condition. switching noise of both ports 0 and 1 together might trigger the lvd flag. table 15. rom selectable options port 00?03 pull-ups on/off port 04?07 pull-ups on/off port 20?27 pull-up port 3 pull-ups on/off port 3 pull-ups on/off watchdog timer at power-on reset on/off field bit position description lvd 765432--- reserved -----2 r 1 0* hvd flag set hvd flag reset ------1- r 1 0* lvd flag set lvd flag reset -------0 r/w 1 0* enable vd disable vd *default after por. note: note:
ps021418-0208 functional description crimzon ? zlr16300 product specification 55 voltage detection and flags the voltage detection register (lvd, register 0ch at the expanded register bank 0dh ) offers an option of monitoring the v cc voltage. the voltage detec tion is enabled when bit 0 of lvd register is set. when vo ltage detection is enabled, the v cc level is monitored in real time. the flags in the lvd register valid 20 us after voltage detection is enabled. the hvd flag (bit 2 of the lvd register) is set only if v cc is lower than the v hvd . when voltage detection is enabled, the lvd flag al so triggers irq5. the irq bit 5 latches the low-voltage condition until it is cleared by in structions or reset. the irq5 interrupt is served if it is enabled in the imr register. ot herwise, bit 5 of irq register is latched as a flag only. if it is necessary to receive an lvd interrupt upon power-up at an operating voltage lower than the low battery det ect threshold, enable interrupts us ing the enable interrupt instruc- tion (ei) prior to enabling the voltage detection. expanded register file control registers (0d) the expanded register file contro l registers (0d) are displayed in figure 34 through figure 38 on page 60. ctr0 (0d) 00h d7 d6 d5 d4 d3 d2 d1 d0 0 p34 as port output* 1 timer8 output 0 disable t8 timeout interrupt** 1 enable t8 timeout interrupt 0 disable t8 data capture interrupt** 1 enable t8 data capture interrupt note:
ps021418-0208 functional description crimzon ? zlr16300 product specification 56 figure 34. tc8 control register ((0d) 00h: read/write except where noted) 00 sclk on t8** 01 sclk/2 on t8 10 sclk/4 on t8 11 sclk/8 on t8 r 0 no t8 counter timeout** r 1 t8 counter timeout occurred w 0 no effect w 1 reset flag to 0 0 modulo-n* 1 single pass r 0 t8 disabled * r1 t8 enabled w0 stop t8 w 1 enable t8 *default setting after reset. **default setting after reset. not reset with a stop mode recovery. ctr0 (0d) 00h
ps021418-0208 functional description crimzon ? zlr16300 product specification 57 ctr1 (0d) 01h d7 d6 d5 d4 d3 d2 d1 d0 transmit mode* r/w 0 t16_out is 0 initially* 1 t16_out is 1 initially capture mode r 0 no falling edge detection r 1 falling edge detection w 0 no effect w 1 reset flag to 0 transmit mode* r/w 0 t8_out is 0 initially* 1 t8_out is 1 initially capture mode r 0 no rising edge detection r 1 rising edge detection w 0 no effect w 1 reset flag to 0 transmit mode* 0 0 normal operation* 0 1 ping-pong mode 1 0 t16_out = 0 1 1 t16_out = 1 capture mode 0 0 no filter 0 1 4 sclk cycle filter 1 0 8 sclk cycle filter 11reserved transmit mode/t8/t16 logic 0 0 and** 01or 1 0 nor 11nand capture mode 0 0 falling edge detection 0 1 rising edge detection 1 0 both edge detection 11reserved transmit mode 0 p36 as port output* 1 p36 as t8/t16_out capture mode 0 p31 as demodulator input 1 p20 as demodulator input
ps021418-0208 functional description crimzon ? zlr16300 product specification 58 figure 35. t8 and t16 common control functions ((0d) 01h: read/write) ensure to differentiate th e transmit mode from captu re mode. depending on the operation of these two modes, the ctr1 bit has diffe rent functions. changing from one mode to another cannot be performed without disabling the counter/ timers. ctr2 (0d) 02h transmit/capture mode 0 transmit mode* 1 capture mode *default setting after reset. **default setting after reset. not reset with a stop mode recovery. d7 d6 d5 d4 d3 d2 d1 d0 0 p35 is port output * 1 p35 is tc16 output 0 disable t16 timeout interrupt* 1 enable t16 timeout interrupt 0 disable t16 data capture interrupt** 1 enable t16 data capture interrupt 0 0 sclk on t16** 0 1 sclk/2 on t16 1 0 sclk/4 on t16 1 1 sclk/8 on t16 ctr1 (0d) 01h notes:
ps021418-0208 functional description crimzon ? zlr16300 product specification 59 figure 36. t16 control register ((0d) 02h: read/write except where noted) ctr3 (0d) 03h figure 37. t8/t16 control register (0d) 03h: read/write (except where noted) r 0 no t16 timeout** r 1 t16 timeout occurs w 0 no effect w 1 reset flag to 0 transmit mode 0 modulo-n for t16* 1 single-pass for t16 capture mode 0 t16 recognizes edge 1 t16 does not recognize edge r 0 t16 disabled * r 1 t16 enabled w 0 stop t16 w1enable t16 *default setting after reset. **default setting after reset. not reset with a stop mode recovery. d7 d6 d5 d4 d3 d2 d1 d0 reserved no effect when written always reads 11111 sync mode 0 disable sync mode** 1 enable sync mode t 8 enable r 0* t 8 disabled r 1 t 8 enabled w 0 stop t 8 w 1 enable t 8 t 16 enable r 0* t 16 disabled r 1 t 16 enabled w 0 stop t 16 w 1 enable t 16 *default setting after reset. **default setting after reset. not reset after stop mode recovery
ps021418-0208 functional description crimzon ? zlr16300 product specification 60 if sync mode is enabled, the first pulse of t8 (carrier) is always synchronized with t16 (demodulated signal). it can always provide a full carrier pulse. lvd (0d) 0ch figure 38. voltage detection register d7 d6 d5 d4 d3 d2 d1 d0 voltage detection 0: disable * 1: enable lvd flag (read only) 0: lvd flag reset * 1: lvd flag set hvd flag (read only) 0: hvd flag reset * 1: hvd flag set reserved (must be 0) *default setting after reset. note:
ps021418-0208 functional description crimzon ? zlr16300 product specification 61 expanded register file control registers (0f) the expanded register file contro l registers (0f) are displayed in figure 39 through figure 52 on page 69. pcon (0f) 00h figure 39. port configuration register (pcon) ((0f)00h: write only)) d7 d6 d5 d4 d3 d2 d1 d0 comparator output port 3 0 p34, p37 standard output * 1 p34, p37 comparator output reserved. (must be 1) port 0 0: open-drain 1: push-pull * reserved (must be 1) *default setting after reset.
ps021418-0208 functional description crimzon ? zlr16300 product specification 62 smr (0f) 0bh figure 40. stop mode recovery register ((0f) 0bh: d6?d0=write only, d7=read only) d7 d6 d5 d4 d3 d2 d1 d0 sclk/tclk divide-by-16 0 off * 1 on reserved (must be 0) stop mode recovery source 000 por only* * 001 reserved 010 p31 011 p32 100 p33 101 p27 110 p2 nor 0?3 111 p2 nor 0?7 stop delay 0off 1 on * * * * stop recovery level * * * 0 low** 1 high stop flag 0 por * * * * * 1 stop recovery * * *default setting after reset. * *set after stop mode recovery. * * *at the xor gate input. * * * *default setting after reset. must be 1 if usi ng a crystal or resonator clock source. not reset with a stop mode recovery. * * * * *default setting after power-on reset.
ps021418-0208 functional description crimzon ? zlr16300 product specification 63 smr2 (0f) 0dh figure 41. stop mode recovery register 2 ((0f) 0dh: d2?d4, d6 write only) d7 d6 d5 d4 d3 d2 d1 d0 reserved (must be 0) reserved (must be 0) stop mode reco very source 2 000 por only * 001 nand p20, p21, p22, p23 010 nand p20, p21, p22, p2 3, p24, p25, p26, p27 011 nor p31, p32, p33 100 nand p31, p32, p33 101 nor p31, p32, p33, p00, p07 110 nand p31, p32, p33, p00, p07 111 nand p31, p32, p33, p20, p21, p22 reserved (must be 0) recovery level * * 0low 1 high reserved (must be 0) note: if used in conjunction with smr, either of the two specified events causes a stop mode recovery. *default setting after reset. not reset with a stop mode recovery. * *at the xor gate input
ps021418-0208 functional description crimzon ? zlr16300 product specification 64 wdtmr (0f) 0fh figure 42. watchdog timer register ((0f) 0fh: write only) standard control registers the standard control registers are displayed in figure 43 through figure 52 on page 69. r246 p2m (f6h) figure 43. port 2 mode register (f6h: write only) d7 d6 d5 d4 d3 d2 d1 d0 wdt tap int rc osc 00 10 ms min. 01 20 ms min.* 10 40 ms min. 11 80 ms min. wdt during halt 0off 1on * wdt during stop 0off 1on * reserved (must be 0) *default setting after reset. not reset with a stop mode recovery. d7 d6 d5 d4 d3 d2 d1 d0 p27?p20 i/o definition 0 defines bit as output 1 defines bit as input * *default setting after reset. not reset with a stop mode recovery.
ps021418-0208 functional description crimzon ? zlr16300 product specification 65 r247 p3m (f7h) figure 44. port 3 mode register (f7h: write only) r248 p01m (f8h) figure 45. port 0 register (f8h: write only) d7 d6 d5 d4 d3 d2 d1 d0 0: port 2 open drain * 1: port 2 push-pull 0= p31, p32 digital mode* 1= p31, p32 analog mode reserved (must be 0) *default setting after reset. not reset with a stop mode recovery. d7 d6 d5 d4 d3 d2 d1 d0 p00?p03 mode 0: output 1: input * reserved (must be 0) reserved (must be 1) reserved (must be 0) p07?p04 mode 0: output 1: input * reserved (must be 0) *default setting after reset; only p00, p01 and p07 are available on 20-pin configurations.
ps021418-0208 functional description crimzon ? zlr16300 product specification 66 r249 ipr (f9h) figure 46. interrupt priority register (f9h: write only) d7 d6 d5 d4 d3 d2 d1 d0 interrupt group priority 000 reserved 001 c > a > b 010 a > b >c 011 a > c > b 100 b > c > a 101 c > b > a 110 b > a > c 111 reserved irq1, irq4, priority (group c) 0: irq1 > irq4 1: irq4 > irq1 irq0, irq2, priority (group b) 0: irq2 > irq0 1: irq0 > irq2 irq3, irq5, priority (group a) 0: irq5 > irq3 1: irq3 > irq5 reserved; must be 0
ps021418-0208 functional description crimzon ? zlr16300 product specification 67 r250 irq (fah) figure 47. interrupt request register (fah: read/write) r251 imr (fbh) figure 48. interrupt mask register (fbh: read/write) d7 d6 d5 d4 d3 d2 d1 d0 irq0 = p32 input irq1 = p33 input irq2 = p31 input irq3 = t16 irq4 = t8 irq5 = lvd inter edge p31 p32 = 00 p31 p32 = 01 p31 p32 = 10 p31 p32 = 11 d7 d6 d5 d4 d3 d2 d1 d0 1 enables irq5?irq0 (d0 = irq0) reserved (must be 0) 0 master interrupt disable * 1 master interrupt enable * * *default setting after reset. * *only by using ei, di instruction; di is required before changing the imr register.
ps021418-0208 functional description crimzon ? zlr16300 product specification 68 r252 flags (fch) figure 49. flag register (fch: read/write) r253 rp (fdh) figure 50. register pointer (fdh: read/write) d7 d6 d5 d4 d3 d2 d1 d0 user flag f1 user flag f2 half carry flag decimal adjust flag overflow flag sign flag zero flag carry flag d7 d6 d5 d4 d3 d2 d1 d0 expanded register bank pointer working register pointer default setting after reset = 0000 0000
ps021418-0208 functional description crimzon ? zlr16300 product specification 69 r254 sph (feh) figure 51. stack pointer high (feh: read/write) r255 spl (ffh) figure 52. stack pointer low (ffh: read/write) d7 d6 d5 d4 d3 d2 d1 d0 general-purpose register d7 d6 d5 d4 d3 d2 d1 d0 stack pointer low byte (sp7?sp0)
ps021418-0208 functional description crimzon ? zlr16300 product specification 70
ps021418-0208 electrical characteristics crimzon ? zlr16300 product specification 71 electrical characteristics absolute maximum ratings a stress greater than listed in table 16 may or may not cause permanent damage to the device. functional operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. exposure to absolute maximum rating conditions for an extended period affects device reliability. table 16. absolute maximum ratings parameter minimum stress maximum stress units notes ambient temperature under bias 0 +70 c storage temperature -65 +150 c voltage on any pin with respect to v ss -0.3 +4.0 v 1 voltage on v dd pin with respect to v ss -0.3 +3.6 v maximum current on input and/or inactive output pin -5 +5 ma maximum output current from active output pin -25 +25 ma maximum current into v dd or out of v ss 75 ma 1 this voltage applies to all pins except v dd .
ps021418-0208 electrical characteristics crimzon ? zlr16300 product specification 72 standard test conditions the characteristics listed in this product speci fication apply for standa rd test conditions. all voltages are referenced to gnd. positive current flows in to the referenced pin (see figure 53 ). figure 53. test load diagram dc characteristics table 17 lists the direct current (dc) characteristics. table 17. dc characteristics t a = 0 c to +70 c units conditions notes symbol parameter v cc minimum typ(7) maximum v cc supply voltage 2.0 v 3.6 v see note 5 v ch clock input high voltage 2.0?3.6 v 0.8 v cc v cc +0.3 v driven by external clock generator v cl clock input low voltage 2.0?3.6 v v ss ?0.3 0.5 v driven by external clock generator v ih input high voltage 2.0?3.6 v 0.7 v cc v cc +0.3 v v il input low voltage 2.0?3.6 v v ss ?0.3 0.2 v cc v v oh1 output high voltage 2.0?3.6 v v cc ?0.4 v i oh = ?0.5 ma v oh2 output high voltage (p36, p37, p00, p01) 2.0?3.6 v v cc ?0.8 v i oh = ?7 ma v ol1 output low voltage 2.0?3.6 v 0.4 v i ol = 4.0 ma from output under test 150 pf
ps021418-0208 electrical characteristics crimzon ? zlr16300 product specification 73 v ol2 output low voltage (p00, p01, p36, p37) 2.0?3.6 v 0.8 v i ol = 10 ma v offse t comparator input offset voltage 2.0?3.6 v 25 mv v ref comparator reference voltage 2.0?3.6 v 0 v dd -1.75 v i il input leakage 2.0?3.6 v ?1 1 av in = 0v, v cc pull-ups disabled r pu pull-up resistance 2.0 v 225 675 k ? v in = 0v; pullups selected by mask option 3.6 v 75 275 k ? i ol output leakage 2.0?3.6 v ?1 1 av in = 0v, v cc i cc supply current 2.0 v 3.6 v 1.2 2.1 3 5 ma ma at 8.0 mhz at 8.0 mhz 1 , 2 1 , 2 i cc1 standby current (halt mode) 2.0 v 3.6 v 0.5 0.8 1.6 2.0 ma ma v in = 0v, clock at 8.0 mhz same as above 1 , 2 , 6 1 , 2 , 6 i cc2 standby current (stop mode) 2.0 v 3.6 v 2.0 v 3.6 v 1.2 1.4 3.5 6.5 8 10 20 30 a a a a v in = 0 v, v cc wdt is not running same as above v in = 0 v, v cc wdt is running same as above 3 3 3 3 i lv standby current (low voltage) 0.8 6 a measured at 1.3 v 4 v bo v cc low voltage protection 1.8 2.0 v 8 mhz maximum ext. clk freq. v lvd vcc low-voltage detection 2.4 v v hvd vcc high-voltage detection 2.7 v table 17. dc characteristics (continued) t a = 0 c to +70 c units conditions notes symbol parameter v cc minimum typ(7) maximum
ps021418-0208 electrical characteristics crimzon ? zlr16300 product specification 74 notes 1. all outputs unloaded, inputs at rail. 2. cl1 = cl2 = 100 pf. 3. oscillator stopped. 4. oscillator stops when v cc falls below v bo limit. 5. it is strongly recommended to add a filter capacitor (minimum 0.1 f), physically close to vdd and v ss pins if operating voltage fluctuations are anticipated, su ch as those resulting from driving an ir led. 6. comparators and timers are on. interrupt disabled. 7. typical values shown are at 25 c. table 17. dc characteristics (continued) t a = 0 c to +70 c units conditions notes symbol parameter v cc minimum typ(7) maximum
ps021418-0208 electrical characteristics crimzon ? zlr16300 product specification 75 ac characteristics figure 54 and table 18 on page 76 describe the alternating current (ac) characteristics. figure 54. ac timing diagram clock stop mode recovery source clock setup 1 22 3 3 t in 7 4 5 6 7 irq n 8 9 11 10
ps021418-0208 electrical characteristics crimzon ? zlr16300 product specification 76 table 18. ac characteristics t a =0 c to +70 c 8.0 mhz watchdog timer mode register (d1, d0) no symbol parameter v cc minimum maximum units notes 1 tpc input clock period 2.0?3.6 121 dc ns 1 2 trc,tfc clock input rise and fall times 2.0?3.6 25 ns 1 3 twc input clock width 2.0?3.6 37 ns 1 4 twtinl timer input low width 2.0 3.6 100 70 ns 1 5 twtinh timer input high width 2.0?3.6 3tpc 1 6 tptin timer input period 2.0?3.6 8tpc 1 7 trtin,tftin timer input rise and fall timers 2.0?3.6 100 ns 1 8 twil interrupt request low time 2.0 3.6 100 70 ns 1 , 2 9 twih interrupt request input high time 2.0?3.6 10tpc 1 , 2 10 twsm stop mode recovery width spec 2.0?3.6 12 10tpc ns 3 4 11 tost oscillator start-up time 2.0?3.6 5tpc 4 12 twdt watchdog timer delay time 2.0?3.6 2.0?3.6 2.0?3.6 2.0?3.6 10 20 40 160 ms ms ms ms 0, 0 0, 1 1, 0 1, 1 13 t por power-on reset 2.0?3.6 2.5 10 ms notes 1. timing reference uses 0.9 v cc for a logic 1 and 0.1 v cc for a logic 0. 2. interrupt request through port 3 (p33?p31). 3. smr ? d5 = 1. 4. smr ? d5 = 0.
ps021418-0208 electrical characteristics crimzon ? zlr16300 product specification 77 capacitance table 19 lists the capacitances. table 19. capacitance parameter maximum input capacitance 12 pf output capacitance 12 pf i/o capacitance 12 pf note: t a = 25 c, v cc = gnd = 0 v, f = 1.0 mhz, unmeasured pins returned to gnd.
ps021418-0208 electrical characteristics crimzon ? zlr16300 product specification 78
ps021418-0208 packaging crimzon ? zlr16300 product specification 79 packaging figure 55 through figure 60 on page 84 display package in formation available for all the crimzon zlr16300 device versions. figure 55. 20-pin dip package diagram
ps021418-0208 packaging crimzon ? zlr16300 product specification 80 figure 56. 20-pin soic package diagram
ps021418-0208 packaging crimzon ? zlr16300 product specification 81 figure 57. 20-pin ssop package diagram
ps021418-0208 packaging crimzon ? zlr16300 product specification 82 figure 58. 28-pin soic package diagram
ps021418-0208 packaging crimzon ? zlr16300 product specification 83 figure 59. 28-pin dip package diagram
ps021418-0208 packaging crimzon ? zlr16300 product specification 84 figure 60. 28-pin ssop package diagram contact zilog for the actual bonding diagram and chip -on-board assembly. symbol a a1 b c a2 e millimeter inch min max min max 1.73 0.05 1.68 0.25 5.20 0.65 typ 0.09 10.07 7.65 0.63 1.86 0.0256 typ 0.13 10.20 1.73 7.80 5.30 1.99 0.21 1.78 0.75 0.068 0.002 0.066 0.010 0.205 0.004 0.397 0.301 0.025 0.073 0.005 0.068 0.209 0.006 0.402 0.307 0.030 0.078 0.008 0.070 0.015 0.212 0.008 0.407 0.311 0.037 0.38 0.20 10.33 5.38 7.90 0.95 nom nom d e h l controlling dimensions: mm leads are coplanar within .004 inches. h c detail a e d 28 15 114 seating plane a2 e a q1 a1 b l 0 - 8 detail 'a' note:
ps021418-0208 ordering information crimzon ? zlr16300 product specification 85 ordering information the crimzon zlr16300 is available for 16k, 8k, 4k, 2k, and 1k parts. : memory size part number description 16k zlr16300h2816g 28-pin ssop 16 k rom zlr16300p2816g 28-pin pdip 16 k rom zlr16300s2816g 28-pin soic 16 k rom zlr16300h2016g 20-pin ssop 16 k rom zlr16300p2016g 20-pin pdip 16 k rom zlr16300s2016g 20-pin soic 16 k rom 8k zlr16300h2808g 28-pin ssop 8 k rom zlr16300p2808g 28-pin pdip 8 k rom zlr16300s2808g 28-pin soic 8 k rom zlr16300h2008g 20-pin ssop 8 k rom zlr16300p2008g 20-pin pdip 8 k rom zlr16300s2008g 20-pin soic 8 k rom 4k zlr16300h2804g 28-pin ssop 4 k rom zlr16300p2804g 28-pin pdip 4 k rom zlr16300s2804g 28-pin soic 4 k rom zlr16300h2004g 20-pin ssop 4 k rom zlr16300p2004g 20-pin pdip 4 k rom zlr16300s2004g 20-pin soic 4 k rom 2k ZLR16300H2802G 28-pin ssop 2 k rom zlr16300p2802g 28-pin pdip 2 k rom zlr16300s2802g 28-pin soic 2 k rom zlr16300h2002g 20-pin ssop 2 k rom zlr16300p2002g 20-pin pdip 2 k rom zlr16300s2002g 20-pin soic 2 k rom 1k zlr16300h2801g 28-pin ssop 1 k rom zlr16300p2801g 28-pin pdip 1 k rom zlr16300s2801g 28-pin soic 1 k rom zlr16300h2001g 20-pin ssop 1 k rom zlr16300p2001g 20-pin pdip 1 k rom
ps021418-0208 ordering information crimzon ? zlr16300 product specification 86 for faster results, contact your local zilog ? sales office for assistance in ordering the part(s) required. zlr16300s2001g 20-pin soic 1 k rom development tools zlp128ice01zemg* in-circuit emulator note: *zlp128ice01zemg has been replaced by an im- proved version, zcrmznice01zemg. zcrmznice01zemg crimzon in-circuit emulator zcrmzn00100kitg crimzon in-circuit emulator development kit zcrmznice01zacg 20-pin accessory kit zcrmznice02zacg 40/48-pin accessory kit note: contact www.zilog.com for the die form. memory size part number description
ps021418-0208 ordering information crimzon ? zlr16300 product specification 87 part number description zilog part numbers consist of a number of components as shown below. for example, part number zlr16300h2816g is a crimzon masked rom product in a 28-pin ssop package, with 16 kb of rom and built with lead-free solder. z lr 16300 h 28 16 g environmental flow g = lead free memory size 16 = 16 kb 8 = 8 kb 4 = 4 kb 2 = 2 kb 1 = 1 kb number of pins in package 28 = 28 pins 20 = 20 pins package type h = ssop p = pdip s = soic product number 16300 product line crimzon rom zilog product prefix
crimzon ? zlr16300 product specification ps021418-0208 index 88 index numerics 16-bit counter/timer circuits 36 20-pin dip package diagram 79 20-pin ssop package diagram 81 28-pin dip package diagram 83 28-pin soicpackage diagram 82 28-pin ssop package diagram 84 8-bit counter/timer circuits 32 a ac timing diagram 75 address spaces, basic 1 architecture 1 expanded register file 18 b basic address spaces 1 block diagram 1 , 3 block diagram, zlr16300 functional 3 c capture_int_mask 24 , 28 clock 43 comparator inputs/outputs 13 configuration port 0 8 port 2 9 port 3 10 port 3 counter/timer 12 counter/timer 16-bit circuits 36 8-bit circuits 32 brown-out voltage/standby 54 clock 43 demodulation mode count capture flowchart 34 demodulation mode flowchart 35 eprom selectable options 54 glitch filter circuitry 30 halt instruction 44 input circuit 29 interrupt block diagram 41 interrupt types, sources and vectors 42 oscillator configuration 43 output circuit 39 ping-pong mode 38 port configuration register 45 resets and wdt 53 sclk circuit 47 stop instruction 44 stop mode recovery register 46 stop mode recovery register 2 49 , 50 stop mode recovery source 48 t16 demodulation mode 37 t16 transmit mode 36 t16_out in modulo-n mode 37 t16_out in single-pass mode 37 t8 demodulation mode 33 t8 transmit mode 30 t8_out in modulo-n mode 33 t8_out in single-pass mode 33 transmit mode flowchart 31 voltage detection and flags 55 watchdog timer mode register 51 watchdog timer time select 52 counter/timer functional blocks input circuit 29 t8 transmit mode 30 counter_int_mask 28 crt3 t8/t16 control register register 28 ctr(d)01h t8 and t16 common functions 25 ctr1 (0d)01 24 ctr3 t8/t16 control ctr3(0d)03h 28 d demodulation mode count capture flowchart 34 flowchart 35
crimzon ? zlr16300 product specification ps021418-0208 index 89 t16 37 t8 33 description functional 15 e eprom selectable options 54 expanded register file 17 expanded register file architecture 18 expanded register file control registers 60 flag 68 interrupt mask register 67 interrupt priority register 66 interrupt request register 67 port 0 and 1 mode register 65 port 2 configuration register 64 port 3 mode register 65 port configuration register 64 register pointer 68 stack pointer high register 69 stack pointer low register 69 stop mode recovery register 62 stop mode recovery register 2 63 t16 control register 59 t8 and t16 common control functions register 58 tc8 control register 55 watch-dog timer register 64 f features standby modes 2 zlr16300 1 functional description counter/timer functional blocks 29 ctr0(0d)00h register 23 ctr1(0d)01h register 24 ctr2(0d)02h register 27 expanded register file 17 expanded register file architecture 18 hi16(0d)09h register 22 hi8(0d)0bh register 21 l08(0d)0ah register 22 l0i6(0d)08h register 22 program memory map 16 ram 16 register description 54 register file 20 register pointer 19 register pointer detail 21 stack 21 tc16h(0d)07h register 22 tc16l(0d)06h register 22 tc8h(0d)05h register 23 tc8l(0d)04h register 23 tc8l(d)04h register 23 g glitch filter circuitry 29 , 30 h halt instruction, counter/timer 44 i input circuit 29 interrupt block diagram, counter/timer 41 interrupt types, sources and vectors 42 l low-voltage detection register 54 m memory, program 15 modulo-n mode t16_out 37 t8_out 33
crimzon ? zlr16300 product specification ps021418-0208 index 90 o oscillator configuration 43 output circuit, counter/timer 39 p p34_out 24 p35_out 28 p36_out/demodulator input 26 package information 20-pin dip package diagram 79 20-pin ssop package diagram 81 28-pin dip package diagram 83 28-pin soic package diagram 82 28-pin ssop package diagram 84 part number format 87 pin configuration 20-pin dip/soic/ssop 5 28-pin dip/soic/ssop 6 pin descriptions 5 pin functions port 0 (p07 - p00) 8 port 0 configuration 8 port 2 (p27 - p20) 9 port 2 (p37 - p30) 10 port 2 configuration 9 port 3 configuration 10 port 3 counter/timer configuration 12 xtal1 (time-based input 7 xtal2 (time-based output) 7 ping-pong mode 38 port 0 configuration 8 pin function 8 port 2 configuration 9 pin function 9 port 3 configuration 10 counter/timer configuration 12 port 3 pin function 10 port configuration register 45 power connections 2 power supply 5 precharacterization product 86 program memory 15 map 16 r register 50 ctr0(0d)00h 23 ctr1 (0d) 01 24 ctr1(0d)01h 24 ctr2(0d)02h 27 flag 68 hi16(0d)09h 22 hi8(0d)0bh 21 interrupt priority 66 interrupt request 67 interruptmask 67 l016(0d)08h 22 l08(0d)0ah 22 lvd(d)0ch 54 pointer 68 port 0 and 1 65 port 2 configuration 64 port 3 mode 65 port configuration 45 , 64 stack pointer high 69 stack pointer low 69 stop mode recovery 46 stop mode recovery 2 49 stop mode recovery 62 stop mode recovery 2 63 t16 control 59 t8 and t16 common control functions 58 tc16h(0d)07h 22 tc16l(0d)06h 22 tc8 control 55 tc8h(0d)05h 23 tc8l(0d)04h 23 tc8l(d)04h 23 voltage detection 60 watch-dog timer 64 register description counter/timer2 ls-byte hold 22 counter/timer2 ms-byte hold 22
crimzon ? zlr16300 product specification ps021418-0208 index 91 counter/timer8 control 23 counter/timer8 high hold 23 counter/timer8 low hold 23 ctr2 counter/timer 16 control 27 t16_capture_lo 22 t8 and t16 common functions 24 t8_capture_hi 21 t8_capture_lo 22 register file 20 expanded 17 register pointer 19 detail 21 resets and wdt 53 s sclk circuit 47 single/modulo-n 24 , 28 single-pass mode t16_out 37 t8_out 33 stack 21 standby modes 2 stop instruction, counter/timer 44 stop mode recovery 2 register 49 source 48 stop mode recovery 2 50 stop mode recovery register 46 t t 16 clock 28 t16 enable 28 t16 initial out/falling edge 27 t16 transmit mode 36 t16_capture_hi 22 t8 and t16 common functions 24 t8 clock 24 t8 enable 24 t8 intiial out/rising edge 27 t8 transmit mode 30 t8/t16_logic/edge_detect 26 t8_capture_hi 21 test load diagram 72 time_out 28 timeout 24 timers counter/timer2 ls-byte hold 22 counter/timer2 ms-byte hold 22 counter/timer8 high hold 23 counter/timer8 low hold 23 ctr0 counter/timer8 control 23 t16_capture_hi 22 t16_capture_lo 22 t8_capture_hi 21 t8_capture_lo 22 timing diagram, ac 75 transmit mode flowchart 31 transmit_submode/glitch filter 26 v vcc 5 voltage brown-out/standby 54 detection and flags 55 voltage detection register 60 w watchdog timer mode register watchdog timer mode register 51 time select 52 x xtal1 5 xtal1 pin function 7 xtal2 5 xtal2 pin function 7 z zlr16300 family members 1
ps021418-0208 customer support crimzon ? zlr16300 product specification 92 customer support for answers to technical questions about the product, documentation, or any other issues with zilog?s offerings, please visit zilog?s knowledge base at h ttp://www.zilog.com/kb . for any comments, detail technical questions, or reporting problems, please visit zilog?s technical support at http://support.zilog.com .

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